1. Field of the Invention
The present invention relates to a silicon carbide semiconductor device such as, for example, an insulated gate type field effect transistor and especially a high power vertical MOSFET.
2. Description of the Related Art
A wide variety of vertical MOS transistor and other devices are conventionally known which employ SiC. Examples include those described in Japanese Unexamined Patent Publication No. 4-23977, U.S. Pat. No. 5,323,040, and Shenoy et al., IEEE Electron Device letters, vol. 18, No.3, pp.93-95, March 1997. The vertical MOS transistors disclosed in these documents are designed with high quality materials for high breakdown voltage and low ON resistance compared to MOS transistors formed from silicon.
It is an object of the present invention to provide a SiC MOS transistor which makes full use of the characteristics of SiC in order to obtain even lower ON resistance and higher breakdown voltage than conventional SiC MOS transistors, and which is designed for greater ease of use.
The present invention which achieves the object stated above is a semiconductor device comprising:
a semiconductor substrate comprising silicon carbide of a first conductivity type and a silicon carbide epitaxial layer of the first conductivity type which is formed on the main side of the semiconductor substrate,
a first semiconductor region formed on the main surface of the silicon carbide epitaxial layer and comprising silicon carbide of a second conductivity type,
a second semiconductor region formed on the first semiconductor region, comprising silicon carbide of the first conductivity type and separated from the silicon carbide epitaxial layer of the first conductivity type by the first semiconductor region,
a third semiconductor layer formed on the first semiconductor region, connected to the silicon carbide epitaxial layer and the second semiconductor region, comprising silicon carbide of the first conductivity type, and of higher resistance than the silicon carbide epitaxial layer or semiconductor substrate, and a gate electrode formed on the third semiconductor region with an insulating layer there between,
wherein the third semiconductor layer is depleted when no voltage is being applied to the gate electrode so that said semiconductor device has normally OFF characteristic.
According to this construction, the third semiconductor layer (thin channel epi-layer) is depleted and exhibits a normally OFF characteristic when no voltage is applied to the gate electrode. At such times, the third semiconductor layer must have its depleted layer extending across the full width between the first semiconductor base region and the gate insulating film to exhibit a normally OFF characteristic, but it is not necessary for the depleted layer to extend completely across the entire length of the third semiconductor layer. In particular the depletion of the third semiconductor layer is not necessary where the third semiconductor layer extends to the second semiconductor source region or the region contacting the silicon carbide epitaxial layer of first conductivity type (drift region).
In the construction described above, when a voltage is applied to the gate electrode to form an electric field on the gate insulating layer, an accumulation-type channel is induced on the third semiconductor layer (thin channel epi-layer), and the carrier flows between the source electrode and drain electrode (i.e., an ON state is achieved).
This design can address the low channel mobility problem of conventional inversion mode SiC power transistor, since the device operates in an accumulation mode. It was demonstrated in Si electronic devices that, the accumulation layer channel mobility is much higher than the inversion layer channel mobility (See for example, S. C. Sun et al., IEEE. Trans. Electron Device, Vol.ED-27, pp.1497, 1980). The same can be applied to MOS based SiC power devices. A large reduction in the ON resistance can also be expected for accumulation mode SiC power devices.
The normally OFF characteristic of the third semiconductor layer is achieved by mutually connecting the depleted layer which extends between the gate electrode and the third semiconductor layer, and the depleted layer between the second semiconductor layer and the third semiconductor layer. Thus, according to the silicon carbide semiconductor device of the present invention, the impurity concentration and thickness of the third semiconductor layer, and the second semiconductor region and gate electrode allow total depletion of the third semiconductor layer even when no voltage is being applied to the gate electrode, thus allowing a normally OFF characteristic to be achieved so that it can be used like a conventional normally OFF device.
Furthermore, according to the semiconductor device of the invention, the impurity concentration of the first semiconductor base region and the impurity concentration of the third semiconductor layer in which the channel is formed are independently controlled, to give a silicon carbide semiconductor device with high breakdown voltage, low current loss and a low threshold voltage. That is, the impurity concentration of the first semiconductor region may be increased, so that while maintaining a high breakdown voltage between the source and drain, the depth of the first semiconductor base region can be shorten to reduce the junction field effect (JFET-effect). In addition, since the impurity concentration of the channel may be decreased to reduce the effect of impurity scattering during flow of the carrier, the channel mobility may be thereby increased. As a result it is possible to obtain a silicon carbide semiconductor device with high breakdown voltage and low current losses.
The silicon carbide semiconductor device of the present invention is a planar vertical field effect transistor, but it may also be applied to planar or trench-type transistors.
A planar-type semiconductor device according to the invention comprises the following:
a semiconductor substrate of a first conductivity type comprising single crystal silicon carbide and a silicon carbide epitaxial layer of the first conductivity type which is formed on the main side of the semiconductor substrate and has a lower dopant concentration than the semiconductor substrate,
a first semiconductor base region of a second conductivity type formed on a predetermined region of the silicon carbide epitaxial layer to a predetermined depth,
a second semiconductor source region of the first conductivity type formed on a predetermined region of the base region and having a shallower depth than the base region,
a third semiconductor surface channel layer of the first conductivity-type made of silicon carbide, and situated so as to connect the source region and the silicon carbide epitaxial layer of the first conductivity type and the second semiconductor base region,
a gate insulating layer formed on the surface of the surface channel layer, a gate electrode formed on the surface of the channel layer,
a source electrode formed in contact with the base region and source region, and
a drain electrode formed on the back side of the semiconductor substrate.
The following are preferred embodiments of the planar-type semiconductor device.
(1) The main surface of the silicon carbide semiconductor substrate is (0001) Si face, (000{overscore (1)}) C-face, (11{overscore (2)}0) a-face or (1{overscore (1)}00) prism-face. The (0001) Si face or (11{overscore (2)}0) a-face is preferred for the low interface surface state of the silicon carbide/insulator interface.
(2) The dopant concentration of the surface channel layer is no greater than the dopant concentrations of the silicon carbide epitaxial layer and the base region.
(3) The gate electrode has a first work function potential, the base region has a second work function potential, the surface channel layer has a third workfunction potential, and the first, second and third workfunction potentials are set so that the carrier of the first conductivity type is depleted in the surface channel layer.
(4) The first, second and third work function potentials are set so that the carrier of the first conductivity type is depleted in the surface channel layer when the gate electrode is at zero potential with respect to the drain region.
(5) The surface channel layer is formed by epitaxial growth or ion implantation.
(6) The surface channel layer is formed by epitaxial growth, and the crystal system/polymorph of the silicon carbide constituting the semiconductor substrate, silicon carbide epitaxial layer, base region and source region is different from that of the silicon carbide of the surface channel layer. For example, the silicon carbide constituting the semiconductor substrate, silicon carbide epitaxial layer, base region and source region is a hexagonal system, while the silicon carbide of the surface channel layer is a cubic system.
(7) The surface channel layer is formed by epitaxial growth, and the silicon carbide constituting the semiconductor substrate, silicon carbide epitaxial layer, base region and source region is 6H-SiC while the silicon carbide of the surface channel layer is 3C-SiC.
By using a surface channel layer formed by epitaxial growth where the silicon carbide crystal system/polymorph differs from that of the base as in (5) and (6), it is possible to realize a device with high characteristics and high reliability.
(8) A portion of the first semiconductor base region is made thicker. This allows breakdown to occur more readily.
(9) In the silicon carbide semiconductor device according to (8) above, the impurity concentration of the thickened section of the first semiconductor base region is made higher than the impurity concentration of the thinner sections. This further facilitates breakdown.
(10) In the silicon carbide semiconductor device according to (8) above, the thickened section of the base region may be formed under the source region. This allows common use of the deep base region forming mask and the source region forming mask for production.
(11) A silicon carbide epitaxial layer of a first conductivity type having a lower dopant concentration than the semiconductor substrate is formed on the main surface of the semiconductor substrate of the first conductivity type which is made of single crystal silicon carbide, and a first base region of a second conductivity type having a predetermined depth is formed on a predetermined region of the surface section of the silicon carbide epitaxial layer. In addition, a surface channel layer of the first conductivity type and made of silicon carbide is situated on the silicon carbide epitaxial layer, a second base region of the second conductivity type and with a greater depth than the first base region is formed on a predetermined region with in the first base region, and then the second base region forming mask is used to form a source region of the first conductivity type which has a shallower depth than the first base region, on a predetermined region of the surface section of the first base. Afterwards, a gate electrode is formed on the surface of the surface channel layer with a gate insulating film there between, while a source electrode is formed contacting the base region and source region. Thus, it is possible to form the source region using the second base region forming mask, to allow use of the mask for both purposes.
(12) In the silicon carbide semiconductor device according to (8) above, the thickened section of the base region is formed at a location not overlapping the source region. This helps to prevent the breakdown.
(13) The surface channel layer may be overlapping a portion of the second semiconductor source region. This allows widening of the contact area from the second semiconductor source region to the surface channel layer.
(14) The third semiconductor region has a concentration distribution of said second conductivity-type impurity which is lower at the top surface of said third semiconductor region close to said gate electrode than inside of said third semiconductor region.
(15) In the silicon carbide semiconductor device according to (14), the concentration of said second conductivity-type impurity in said third semiconductor region gradually decreases in the depth direction toward said top surface.
(16) In the silicon carbide semiconductor device according to (15), the second conductivity-type impurity is boron.
(17) In the silicon carbide semiconductor device according to (16), the third semiconductor region is a surface channel layer where a first conductivity-type impurity is ion implanted.
(18) The base region has a recess in a portion of the top surface thereof and has a portion deeper than the other portion thereof which portion resides below said recess and extends closer to said semiconductor substrate.
(19) In the silicon carbide semiconductor device according to (18), the recess is formed in contact with said source region and penetrating said source region.
(20) In the planar-type semiconductor device, the section of the surface channel layer which is situated on the surface section of the silicon carbide epitaxial layer may be made with lower resistance than the silicon carbide epitaxial layer to allow still further reduction in the ON resistance of the MOSFET in accumulation mode. The ON resistance of the MOSFET is determined by the contact resistance between the source electrode and source region, the internal resistance of the source region, the accumulation channel resistance in the channel region formed on the surface channel layer, the internal resistance of the accumulation drift resistance of surface channel layer, the JFET resistance of the JFET section, the internal resistance of the epitaxial layer, the internal resistance of the semiconductor substrate, and the contact resistance between the semiconductor substrate and the drain electrode, their sum constituting the ON resistance.
Consequently, by making the impurity concentration of the section of the surface channel layer situated on the surface section of the epitaxial layer to be higher than that of the epitaxial layer, it is possible to lower the resistance of the sections of the surface channel layer other than the channel region (accumulation-drift resistance of channel layer), thus lowering the ON resistance of the MOSFET. This allows an even lower ON resistance to be achieved for the MOSFET.
For example, if the surface channel layer is formed by ion implantation and ion implantation is also carried out in the sections of the surface channel layer other than the channel region, then the impurity concentration of the section of the surface channel layer situated on the surface section of the epitaxial layer may be increased above the impurity concentration of the epitaxial layer, simultaneously with formation of the surface channel layer. This allows simplification of the production process for the silicon carbide semiconductor device.